In this specification, the term “integrated circuit” is used to describe a chip or MCM (multi-chip module) embedded with DFT (design-for-test) techniques.
An integrated circuit or circuit assembly generally contains multiple clocks, which are either generated internally or supplied externally. Each clock is distributed to a set of storage elements via a skew-minimized network, which supplies clock pulses to all storage elements essentially at the same time. Such a clock, its related storage elements, and all combinational logic blocks bounded by these storage elements, form a clock domain. While the clock skew within a single clock domain is designed to be negligible, the clock skew between different clock domains is unbounded and can vary greatly for different storage elements.
Scan-based design is the most widely used design-for-test (DFT) approach for producing high-quality integrated circuits. Scan-based design requires that all storage elements in an integrated circuit, such as D flip-flops, be replaced with their scan-equivalent storage elements, such as Scan D flip-flops, otherwise known as scan cells. These scan cells are connected to form one or more scan chains, with each scan chain being controlled by one or more scan enable (SE) signals and capture clocks (CK) each belonging to a separate clock or frequency domain.
Testing a scan-based integrated circuit proceeds in a sequence of shift-in/shift-out operation and capture operation, repeated for a predetermined number of test patterns. During the shift operation, scan enable (SE) signals, local to all scan cells in a clock domain, are used to configure all scan cells in an integrated circuit into scan chains by selecting the scan data inputs as the input source of all scan cells in the scan chains, and a predetermined stimuli during scan-test or a pseudorandom stimuli during self-test is shifted serially through the scan chains into all scan cells in the circuit. During the capture operation, the scan enable (SE) signal is used to select the data inputs as the input source of all scan cells to test the functional path of the circuit using the stimulus loaded during the shift operation.
Automatic test pattern generation (ATPG) and fault simulation are used to generate the scan test patterns, and to measure their fault coverage respectively. In order to simplify the ATPG and fault simulation process, an event-based logic simulator, as opposed to a timing logic simulator, is embedded within the ATPG and fault simulation engine, used to perform the logic simulation of the capture operation of the scan based test. This makes it impossible to apply the capture clocks of different clock domains simultaneously during the capture operation and simulate the results, since the clock skew between different clock domains would result in incorrect values being captured into some scan cells in the event-based simulation. Different approaches for applying the capture clocks during the capture operation have been developed in order to get around this problem.
Prior-art solution #1, see FIG. 2, is commonly referred to as the one-hot method. In this method all capture clocks are used during the shift operation to set up the stimulus, but only one capture clock is applied during each capture operation. Multiple patterns are used to test the logic paths connected to scan cells belonging to different clock domains. The main advantage of this method is the simplicity in implementing the ATPG and fault simulation engine. The main disadvantage of this method is that a large number of test patterns are required to test the circuit, since only one clock domain can be tested in any given pattern. This further results in longer test time and larger test data volume, which increases the total test cost.
Prior-art solution #2, see FIG. 3, is described in U.S. Pat. No. 6,195,776 by Ruiz et al. (2001). In this approach, a clock order is used to apply selected capture clocks sequentially during the capture operation. However, during ATPG and fault simulation, these capture clocks are simulated in parallel while selectively setting unknown values (‘X’) on different logic paths, depending on the clock order. This guarantees that the results of the parallel cycle-based simulation will match the results of the sequential application of the clocks during the actual capture operation of the test pattern. The main advantage of this approach is that it achieves the same fault coverage as prior-art #1 using a smaller set of test vectors and reduced CPU time. The main disadvantage of this approach is that the test size is still large, since the ATPG and fault simulator are pessimistic in calculating the fault coverage of different scan test patterns due to the unknown values.
Prior-art solution #3, see FIG. 4, is described by Lin et al. In this approach, a clock order is used to apply selected capture clocks sequentially during the capture operation. Multi-timeframe ATPG and fault simulation is used during the capture operation to calculate the exact fault coverage of the test patterns applied. The main advantage of this approach is that the test size is smaller than the previous two approaches, and can approach the optimal set of test vectors, provided that all clocks are applied during the capture operation of the ATPG and fault simulation. In practice, this is difficult to perform, since it results in a dramatic increase in CPU time requirements. In practice, the number of clocks that can be applied is limited, resulting in a sub-optimal set of test patterns using longer CPU time.
Prior-art solution #4, see FIG. 5, is described in U.S. patent application No. 20020184560 by Wang et al. In this approach, a clock order is used to apply selected capture clocks sequentially during the capture operation. A circuit expansion process is used to transform the circuit into an equivalent combinational circuit model, where logic paths are expanded to simulate the results of a multi-timeframe simulation with a single time-frame simulation of the expanded circuit. The main advantage of this approach is that its test size is small, and approaches the optimum set of test vectors for any given circuit. Furthermore, this is accomplished with a realistic increase in memory size, as opposed to an unrealistic increase in CPU time as in prior-art #3. The main disadvantage of this approach is that the increase in memory size might prevent the circuit from being able to fit within a given system memory, and might become un-reasonable as design size continues to grow.
Therefore, there is a need for an improved ATPG and fault simulation, comprising a method and a computer-aided design (CAD) system, that is capable of achieving high fault coverage using an optimum set of test vectors within reasonable memory size and CPU time.